Digital Systems Courses

Over the years, design of digital systems has changed from paper and pencil methods of 60s and 70s to using complex simulation and synthesis tools. Advancements in design abstraction level and hardware description languages (HDLs) have been the center point of this evolutionary process. While today’s most common digital design abstraction is at the register transfer level (RTL), the technology is rapidly moving toward the more abstract design that is electronic system level (ESL).

The primary focus of digital system designers at the RT level is using arithmetic and logic components for processing logical data, and using registers and busses for storing and routing data. On the other hand designers at the system level (ESL) are more concerned with manipulation of large blocks of data by complex processors and processing elements, and moving them through communication switches and routers. At the same time, there have been significant changes in hardware description languages as we move from RTL to ESL. While the dominant languages for simulation and synthesis of RT level of designs have been VHDL and Verilog, the IEEE standard std. 1666 SystemC and its derivatives have emerged as the language for system level simulation, verification and high level synthesis.

For preparing digital system designers for today’s challenging designs, and for enabling them to move forward as the technology changes, the UIC Master of Engineering program has developed courses in Digital Systems design focused on digital system design with VHDL, design and implementation of embedded systems, advanced design and test topics, and system level design with SystemC.

Digital Systems Courses:

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